1. Field Of The Invention
The invention relates generally to semiconductor logic test systems especially those logic test systems used to test for shorts in complementary metal oxide semiconductor (CMOS) transistor circuits and more particularly, to a fast recovery power supply for supplying a high current to a CMOS device under test and for measuring the low current of the device while it is under test.
2. Description of the Prior Art
Microprocessors employ large numbers of logic circuits. To test such microprocessors a technique known as Level Sensitive Scan Device (LSSD) testing was developed. This technique has been described, for example in U.S. Pat. No. 3,761,695; U.S. Pat. No. 4,441,075; Electronics Mar. 10, 1983, pgs. 110-115; and Electronics Mar. 15, 1979, pgs. 10-11.
This LSSD testing is satisfactory to measure for all defects in CMOS transistor circuits except for a defect which represents a unique failure mechanism known as the shorted fault. Such shorted faults are usually but not always source to drain shorts.
The present apparatus is particularly designed to test for such shorted faults.